OmniXtend: Scalable Memory Disaggregation over Ethernet
Welcome to the official documentation site for OmniXtend, an open and scalable memory interconnect architecture designed to enable cache-coherent memory disaggregation over standard Ethernet infrastructure.
OmniXtend connects CPUs, accelerators, and memory modules using packet-based communication, enabling flexible system composition and efficient resource sharing across nodes. This site provides a comprehensive guide to OmniXtend’s architecture, hardware, software stack, and use cases.
🔍 What is OmniXtend?
OmniXtend is an open memory interconnect protocol that:
- Uses standard Ethernet to build coherent memory systems
- Supports TileLink as its coherence protocol
- Enables disaggregated memory access across compute elements
- Scales from embedded systems to datacenter environments
It is especially suited for:
- Machine learning workloads requiring large memory pools
- Edge computing clusters with shared memory
- Open hardware research and experimentation
🚀 Key Features
- ✅ Cache-coherent access over Ethernet
- 🔌 Hardware-friendly: Integrates with FPGA and RISC-V platforms
- 🌐 Standards-based: Uses UDP/Ethernet framing for wide compatibility
- 🧠 Open and Extensible: Built on open-source protocols like TileLink
- 📦 Chipyard integration for rapid prototyping
📚 Documentation Structure
- Overview: Background, goals, and architecture
- Getting Started: Quickstart with hardware and tools
- Architecture: Protocol, packet format, memory model
- Hardware Setup: Board configurations and design
- Software Stack: Drivers, firmware, integration
- Tutorials: Step-by-step guides and examples
- Use Cases: Real-world applications
- Developer Guide: For contributors and advanced users
- Publications: Papers, etc.
- References: References
📦 Source Code
- GitHub Repository: github.com/etri/omnixtend
- Bug Reports / Issues: Use the Issue Tracker
💬 Stay Connected
- 📬 Contact: seungjunn@gmail.com
- 💬 Join the discussion on Slack (link coming soon)